Strained transistor with hybrid-strain inducing layer
US7164163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Feb 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.