Memory circuit with spacers between ferroelectric layer and electrodes
US7164166B2 · kind B2 · utility
0Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
Abstract
A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.