Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
US7164174B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.