Techniques for reducing bowing in power transistor devices
US7164200B2 · kind B2 · utility
4Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Aug 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
Abstract
Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.