Device and method for using dynamic cell plate sensing in a DRAM memory cell
US7164595B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are each configured in series for individual respective coupling between a first digit line and a second digit line. The first and second pass transistors are further configured for respective control by first and second wordlines. The first pass transistor and first capacitor are symmetrically configured with the second pass transistor and the second capacitor. The memory cell further includes an interconnection formed on a cell plate conductor between a terminal end of the first capacitor and a terminal end of the second capacitor. Furthermore, the interconnection is electrically isolated from other portions of the cell plate conductor. The memory device further includes a plurality of sense amplifiers configured for selectably coupling with pairs of the first and second digit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.