SRAM cell with column select line
US7164596B1 · kind B1 · utility
41Cited by
10References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.