Reverse fowler-nordheim tunneling programming for non-volatile memory cell
US7164606B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2005 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Jul 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array that are to be programmed, all the electrodes of the cell are grounded. Then, an inhibiting voltage Vn is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or remain at the inhibiting voltage Vn. For all cells in the NVM array that are not selected for programming, the inhibiting voltage Vn is applied to Vr, Ve and Dr and is also applied to Vp, Dp and Vnw. The control gate voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control gate voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inh…
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