Scan chain disable function for power saving
US7165006B2 · kind B2 · utility
3Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | May 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.