Load store unit with replay mechanism
US7165167B2 · kind B2 · utility
5Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Sep 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.