Edge termination for silicon power devices

US7166866B2 · kind B2 · utility

Assignee

• Intersil Americas LLC · US

Inventors

• Jun Zeng · Torrance, US
• Gary Mark Dolry · Smethport, US
• Praveen MurAleedharan · Wilkes-Barre, US

Key dates

• Filing date: Jul 2, 2004
• Grant date: Jan 23, 2007
• Expiry date: Oct 11, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/931

Abstract

A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.