Delay circuitry and method therefor
US7167035B2 · kind B2 · utility
5Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2005 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Apr 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.