Varactor with improved tuning range
US7169679B2 · kind B2 · utility
3Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Aug 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
Abstract
A varactor has a plurality of alternating P− wells and N+ regions formed in a silicon layer. Each of the P− wells forms a first N+/P− junction with the N+ region on one of its side and a second N+/P− junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P− wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.