Method for fabricating a metal-insulator-metal capacitor
US7169680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a capacitor is disclosed. First, a dielectric layer is disposed on a semiconductor substrate. Next, at least one dual damascene opening and at least one capacitor opening are formed in the dielectric layer. Next, a first conductive layer is disposed on the surface of the dielectric layer, the bottom and sidewall of the capacitor opening, and the dual damascene opening. Next, an insulating layer is formed on the first conductive layer and a second conductive layer is disposed on the insulating layer. Following that, a planarization process is performed to remove the second conductive layer, the insulating layer, and the first conductive layer on the dielectric surface for forming a capacitor and a dual damascene conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.