Arrangement and method for ESD protection
US7170135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2003 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vtl for ESD protection. Vtl can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.