Bump for semiconductor package, semiconductor package applying the bump, and method for fabricating the semiconductor package
US7170170B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Dec 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a bump for a semiconductor package, a semiconductor package applying the bump, and a method for fabricating the semiconductor package. As a second bump unit contacting an electrode terminal of a PCB has a smaller width than a first bump unit contacting an electrode pad of a semiconductor chip through a metal adhering layer, even if a pitch between the electrode pads of the semiconductor chip does not correspond to the pitch between the electrode terminals of the PCB, contact reliability is improved by the bump. In addition, the bump does not contact lines adjacent to the electrode terminal of the PCB, thereby preventing a mis-operation of the semiconductor package. Accordingly, the pitch between the electrode pads of the semiconductor chip and the pitch between the bumps can be minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.