Semiconductor device
US7170176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Nov 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection includes a columnar conductive member and the upper and lower layers thereof and each of the lower layer and the upper layer is formed of a conductive layer formed over the entire lower-layer wiring. The upper-layer is electrically connected to the lower-layer wiring in the portion where the projection is exposed substantially on the same plane as the top surface of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.