Programmable logic array latch
US7170316B2 · kind B2 · utility
2Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jan 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.