Patent · US Expired

Methods of screening ASIC defects using independent component analysis of quiescent current measurements

US7171638B2 · kind B2 · utility

0Cited by
16References
10Claims
0Family size

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Key dates

Filing dateOct 20, 2004
Grant dateJan 30, 2007
Priority date
Expiry dateMay 15, 2025

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/3008
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.