Fabrication of semiconductor interconnect structures
US7172497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2002 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC25D17/001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.