Chromeless phase mask layout generation
US7172838B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.