Method to avoid a laser marked area step height
US7172948B2 · kind B2 · utility
3Cited by
6References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2004 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.