Manufacturing method of semiconductor integrated circuit device that includes chemically and mechanically polishing two conductive layers using two polishing pads that have different properties
US7172963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2004 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent, which controls the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less, is used as the slurry, and the pad which is made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253 and which is comprised of the foam including non-uniform pores with a diameter of about 150 μm or larger and a density of about 0.4–0.16 g/cm3, is used as the polishing pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.