Semiconductor memory device for enhancing refresh operation in high speed data access
US7174418B2 · kind B2 · utility
2Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40618
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.