Method for extending the local memory address space of a processor
US7174429B2 · kind B2 · utility
16Cited by
9References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | May 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.