Processor power and energy management
US7174469B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for managing power and energy expenditures in cores of a processor to balance performance with power and energy dissipation are disclosed. Embodiments may include pre-decoder(s) between levels of cache or between main memory and a level of cache to monitor core execution rates by associating power tokens with each instruction. The power tokens include values representing the average power dissipated by the core for instructions and a sum of the power tokens may be compared with a state of management control bits for performance, energy, and power, to determine whether to increase or decrease power dissipation in the core. The power dissipation is varied by, e.g., adjusting the issue rate of instructions, adjusting the execution rate of instructions, turning off unused units within the core, controlling the frequency and voltage of the core, and switching tasks between cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.