Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
US7176084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jun 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.