Tsung-Lin Lee
136Patents
16h-index
96Co-inventors
89Inventor score
Filing activity: Apr 25, 2001 → Jun 26, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9171929B2 | Strained structure of semiconductor device and method of making the strained structure | Electricity | 534 | Active |
| US8847293B2 | Gate structure for semiconductor device | Electricity | 490 | Active |
| US8497528B2 | Method for fabricating a strained structure | Electricity | 230 | Active |
| US8610240B2 | Integrated circuit with multi recessed shallow trench isolation | Electricity | 189 | Active |
| US8946828B2 | Semiconductor device having elevated structure and method of manufacturing the same | Electricity | 82 | Active |
| US7176084B2 | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory | Electricity | 61 | Expired |
| US8941153B2 | FinFETs with different fin heights | Electricity | 40 | Active |
| US8174073B2 | Integrated circuit structures with multiple FinFETs | Electricity | 38 | Active |
| US7482236B2 | Structure and method for a sidewall SONOS memory device | Emerging Cross-Sectional Technologies | 35 | Active |
| US8373238B2 | FinFETs with multiple Fin heights | Electricity | 35 | Active |
| US8110466B2 | Cross OD FinFET patterning | Electricity | 35 | Active |
| US8519481B2 | Voids in STI regions for forming bulk FinFETs | Electricity | 30 | Active |
| US9953885B2 | STI shape near fin bottom of Si fin in bulk FinFET | Electricity | 24 | Active |
| US8338305B2 | Multi-fin device by self-aligned castle fin formation | Electricity | 23 | Active |
| US8445340B2 | Sacrificial offset protection film for a FinFET device | Electricity | 20 | Active |
| US8748993B2 | FinFETs with multiple fin heights | Electricity | 16 | Active |
| US8673709B2 | FinFETs with multiple fin heights | Electricity | 16 | Active |
| US8653608B2 | FinFET design with reduced current crowding | Electricity | 12 | Active |
| US9761666B2 | Strained channel field effect transistor | Electricity | 11 | Active |
| US9263342B2 | Semiconductor device having a strained region | Electricity | 11 | Active |
| US9147594B2 | Method for fabricating a strained structure | Electricity | 10 | Active |
| US9847334B1 | Structure and formation method of semiconductor device with channel layer | Electricity | 10 | Active |
| US8723271B2 | Voids in STI regions for forming bulk FinFETs | Electricity | 10 | Active |
| US7133479B2 | Frequency synchronization apparatus and method for OFDM systems | Electricity | 9 | Expired |
| US10374059B2 | Structure and formation method of semiconductor device structure with nanowires | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.