Vertical dual gate field effect transistor

US7176089B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• Steven J. Holmes · Colchester, US
• David V. Horak · South Burlington, US
• James M. Leas · South Burlington, US
• William H. Ma · Wappingers Falls, US
• Paul A. Rabidoux · Winooski, US

Key dates

• Filing date: May 26, 2004
• Grant date: Feb 13, 2007
• Expiry date: Sep 30, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/611
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.