Method for multiple spacer width control

US7176137B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Baw-Ching Perng · Hsinchu, TW
• Yih-Shung Lin · Carrollton, US
• Ming-Ta Lei · Jinshanmian, TW
• Ai-Sen Liu · Hsinchu, TW
• Chia-Hui Lin · Baoshan, TW
• Cheng-Chung Lin · Taipei, TW

Key dates

• Filing date: May 9, 2003
• Grant date: Feb 13, 2007
• Expiry date: Dec 25, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.