In situ doped embedded sige extension and source/drain for enhanced PFET performance

US7176481B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Huajie Chen · Danbury, US
• Dureseti Chidambarrao · Weston, US
• Siddhartha Panda · Beacon, US
• Sang-Hyun Oh · Plymouth, US
• Henry K. Utomo · Ridgefield, US
• Werner Rausch · Hopewell Junction, US

Key dates

• Filing date: Jan 12, 2005
• Grant date: Feb 13, 2007
• Expiry date: Jan 12, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.