Semiconductor integrated circuit
US7176487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Apr 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.