SiGe MOSFET with an erosion preventing Six1Gey1 layer
US7176504B1 · kind B1 · utility
3Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer is deposited on the sidewalls of the gate structure. The SixGey layer is deposited in the substrate on both sides of the spacer and extended to a portion beneath part of the spacer. In addition, the top level of the SixGey layer is higher than the surface of the substrate. Moreover, the SixGey protection layer is deposited on the SixGey layer and the SixGey protection layer comprises Six1Gey1, where 0≦y1<y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.