Damascene patterning of barrier layer metal for C4 solder bumps
US7176583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Feb 21, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.