Multi-stage output buffer
US7176758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Sep 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45706
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-stage output buffer is disclosed. The output buffer includes an emitter follower circuit coupled to a differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit. The buffer further includes a base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit reduces a load impedance at the output of the emitter coupled pair circuit, improves decoupling of the external load from an input circuit when coupled thereto, and increases the output power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.