Method of operating a flash memory device
US7177192B2 · kind B2 · utility
33Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.