Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device
US7177198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.