Word line driving circuit of semiconductor memory device
US7177226B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.