Method and system for cache power reduction
US7177981B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2003 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After accessing each tag array, a selected data array is identified, and subsequently activated. At least one predetermined data entry from the activated data array is accessed, wherein all other data arrays are deactivated during the read operation. In another example, the cache memory is divided into multiple sub-groups so that only a particular sub-group is involved in a memory read operation. By deactivating any many circuits as possible throughout the read operation, the power consumption of the cache memory is greatly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.