Halting clock signals to input and result latches in processing path upon fetching of instruction not supported
US7178046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Apr 1, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.