High-speed level sensitive scan design test scheme with pipelined test clocks

US7178075B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James D. Warnock · Somers, US
• William V. Huott · Holmes, US

Key dates

• Filing date: Apr 25, 2005
• Grant date: Feb 13, 2007
• Expiry date: Jun 9, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.