Testing apparatus and testing method for an integrated circuit, and integrated circuit
US7178078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.