Method for offsetting a silicide process from a gate electrode of a semiconductor device
US7179745B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0323
Abstract
A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.