Methods and structures for planar and multiple-gate transistors formed on SOI
US7180134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jul 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.