Bipolar transistor with a very narrow emitter feature
US7180157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Aug 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/133
Abstract
A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.