Stackable electronic assembly
US7180165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Sep 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.