Laser powered clock circuit with a substantially reduced clock skew
US7180379B1 · kind B1 · utility
262Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.