Semiconductor memory device including 4TSRAMs
US7180768B2 · kind B2 · utility
3Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of improving stability of a memory cell in read mode in an SRAM including a memory cell comprising two access MOS transistors and two drive MOS transistors. The magnitude of voltage between gate and source of an access transistor of a memory cell connected to a selected word line is controlled to be smaller than a power-supply voltage by controlling the voltage of selected word line WL in read mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.