Phase error corrector and method
US7180960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Mar 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0067
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase error corrector circuit and method are disclosed. In one embodiment, a phase error corrector circuit delays a PSK modulated signal and multiplies the delayed PSK modulated signal by the PSK modulated signal in order to generate a forward phase correction signal. The input signal is then mixed with the forward phase correction signal. In another embodiment, a phase error corrector circuit calculates a forward phase offset of a complex PSK modulated signal. The complex PSK modulated signal is phase shifted in a mixer by a phase difference offset in order to generate a phase corrected signal. A backward phase correction means calculates a backward phase offset based on the phase corrected signal. A subtractor subtracts the forward phase offset from the backward phase offset for outputting a difference phase offset to the mixer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.