Patent · US Expired

Method for synchronizing a cache memory with a main memory

US7181576B2 · kind B2 · utility

7Cited by

13References

26Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Berndt Gammel · Borgo San Lazzaro, DE
Thomas Kunemund · Birkenfeld, DE
Holger Sedlak · Hersbruck, DE

Key dates

Filing date	May 27, 2004
Grant date	Feb 20, 2007
Priority date	—
Expiry date	Apr 9, 2025

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0804
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.