Method for page sharing in a processor with multiple threads and pre-validated caches
US7181590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2003 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Oct 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.